Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits

摘要

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizesdown to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOSfoundry. This process is the core of several nodes of a roadmap forfully-planarized fabrication processes for superconductor integrated circuitswith 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. Theprocess utilizes 248 nm photolithography, anodization, high-density plasmaetching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$interlayer dielectric. JJ electric properties and statistics such as on-chipand wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$,and run-to-run reproducibility have been measured on 200-mm wafers over a broadrange of JJ diameters from 200 nm to 1500 nm and critical current densities,$J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted.Diffraction-limited photolithography of JJs is discussed. A relationshipbetween JJ mask size, JJ size on wafer, and the minimum printable size forcoherent and partially coherent illumination has been worked out. The $G_N$ and$I_c$ spreads obtained have been found to be mainly caused by variations of theJJ areas and agree with the model accounting for an enhancement of mask errorsnear the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm downto 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects forcircuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJdefinition are discussed.